Address code generation for digital signal processors

S. Udayanarayanan, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations


In this paper we propose a procedure to generate code with minimum number of addressing instructions. We analyze different methods of generating addressing code for scalar variables and quantify the improvements due to optimizations such as offset assignment, modify register optimization and address register assignment. We propose an offset assignment heuristic that uses k address registers, an optimal dynamic programming algorithm for modify register optimization, and an optimal formulation and a heuristic algorithm for the address register assignment problem.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Number of pages6
StatePublished - 2001
Event38th Design Automation Conference - Las Vegas, NV, United States
Duration: Jun 18 2001Jun 22 2001


Other38th Design Automation Conference
Country/TerritoryUnited States
CityLas Vegas, NV

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


Dive into the research topics of 'Address code generation for digital signal processors'. Together they form a unique fingerprint.

Cite this