TY - GEN
T1 - A wide locking-range, low phase-noise and high output power D-Band SiGe PLL
AU - Zeinolabedinzadeh, Saeed
AU - Song, Ickhung
AU - Kaynak, Mehmet
AU - Cressler, John D.
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/1
Y1 - 2020/1
N2 - A fully integrated, wide locking-range fundamental frequency SiGe phase-locked-loop (PLL) at D-band is proposed which utilizes coupled voltage-controlled-oscillators (VCOs) to generate and distribute balanced RF signals in a symmetric and compact form factor. The proposed technique facilitates the balanced LO distribution, increases the output power, improves the phase noise, and increases the locking range of frequency dividers at the same time, all at the cost of increased DC power consumption. The designed VCO achieves better than 10% DC-to-RF conversion efficiency across the entire tuning-range and provides output power of better than +8 dBm. The VCO achieves a FoMt of more than 194, which, to the best of our knowledge is the highest FoMt among the reported D-band VCOs. The PLL was fully integrated in a 130 nm SiGe BiCMOS technology. This PLL locks at 105-117 GHz. It achieves a phase noise of better than -100 dBc/ Hz and -121 dBc/ Hz at 1 MHz and 10 MHz offset from a 116 GHz carrier, respectively. The measured average output power is better than +8 dBm across the entire locking-range.
AB - A fully integrated, wide locking-range fundamental frequency SiGe phase-locked-loop (PLL) at D-band is proposed which utilizes coupled voltage-controlled-oscillators (VCOs) to generate and distribute balanced RF signals in a symmetric and compact form factor. The proposed technique facilitates the balanced LO distribution, increases the output power, improves the phase noise, and increases the locking range of frequency dividers at the same time, all at the cost of increased DC power consumption. The designed VCO achieves better than 10% DC-to-RF conversion efficiency across the entire tuning-range and provides output power of better than +8 dBm. The VCO achieves a FoMt of more than 194, which, to the best of our knowledge is the highest FoMt among the reported D-band VCOs. The PLL was fully integrated in a 130 nm SiGe BiCMOS technology. This PLL locks at 105-117 GHz. It achieves a phase noise of better than -100 dBc/ Hz and -121 dBc/ Hz at 1 MHz and 10 MHz offset from a 116 GHz carrier, respectively. The measured average output power is better than +8 dBm across the entire locking-range.
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U2 - 10.1109/SIRF46766.2020.9040189
DO - 10.1109/SIRF46766.2020.9040189
M3 - Conference contribution
AN - SCOPUS:85083189702
T3 - 2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020
SP - 35
EP - 38
BT - 2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2020
Y2 - 26 January 2020 through 29 January 2020
ER -