TY - JOUR
T1 - A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS
AU - Jeon, Dongsuk
AU - Seok, Mingoo
AU - Chakrabarti, Chaitali
AU - Blaauw, David
AU - Sylvester, Dennis
N1 - Funding Information:
Manuscript received April 22, 2011; revised June 27, 2011; accepted August 22, 2011. Date of publication November 04, 2011; date of current version December 23, 2011. This paper was approved by Guest Editor Tanay Karnik. This work was supported by the Multiscale Systems Center, Army Research Laboratory, National Science Foundation, and National Institute of Standards and Technology. D. Jeon, D. Blaauw, and D. Sylvester are with the University of Michigan, Ann Arbor, MI 48109-2121 USA (e-mail: djeon@umich.edu). M. Seok is with Texas Instruments, Dallas, TX 75243 USA. C. Chakrabarti is with Arizona State University, Tempe, AZ 85287 USA. Digital Object Identifier 10.1109/JSSC.2011.2169311
PY - 2012/1
Y1 - 2012/1
N2 - This paper proposes a design approach targeting circuits operating at extremely low supply voltages, with the goal of reducing the voltage at which energy is minimized, thereby improving the achievable energy efficiency of the circuit. The proposed methods accomplish this by minimizing the circuit's ratio of leakage to active current. The first method, super pipelining, increases the number of pipeline stages compared to conventional ultra low voltage (ULV) pipelining strategies, reducing the leakage/dynamic energy ratio and simultaneously improving performance and energy efficiency. Measurements of super-pipelined multipliers demonstrate 30% energy savings and 1.6× performance improvement. Since super pipelining reduces the logic depth between registers, two-phase latch based design is employed to compensate for reduced averaging effects and provide better variation tolerance. The second technique introduces a parallel-pipelined architecture that suppresses leakage energy by ensuring full utilization of functional units and reduces memory size. We apply these techniques to a 16-b 1024-pt complex-valued Fast Fourier Transform (FFT) core along with low-power first-in first-out (FIFO) design and robust clock distribution network. The FFT core is fabricated in 65 nm CMOS and consumes 15.8 nJ/FFT with a clock frequency of 30 MHz and throughput of 240 Msamples/s at V dd=270 mV, providing 2.4× better nergy efficiency than current state-of-art and > 10× higher throughput than typical ULV designs. Measurements of 60 dies show modest frequency (energy) σ/μ spreads of 7% (2%).
AB - This paper proposes a design approach targeting circuits operating at extremely low supply voltages, with the goal of reducing the voltage at which energy is minimized, thereby improving the achievable energy efficiency of the circuit. The proposed methods accomplish this by minimizing the circuit's ratio of leakage to active current. The first method, super pipelining, increases the number of pipeline stages compared to conventional ultra low voltage (ULV) pipelining strategies, reducing the leakage/dynamic energy ratio and simultaneously improving performance and energy efficiency. Measurements of super-pipelined multipliers demonstrate 30% energy savings and 1.6× performance improvement. Since super pipelining reduces the logic depth between registers, two-phase latch based design is employed to compensate for reduced averaging effects and provide better variation tolerance. The second technique introduces a parallel-pipelined architecture that suppresses leakage energy by ensuring full utilization of functional units and reduces memory size. We apply these techniques to a 16-b 1024-pt complex-valued Fast Fourier Transform (FFT) core along with low-power first-in first-out (FIFO) design and robust clock distribution network. The FFT core is fabricated in 65 nm CMOS and consumes 15.8 nJ/FFT with a clock frequency of 30 MHz and throughput of 240 Msamples/s at V dd=270 mV, providing 2.4× better nergy efficiency than current state-of-art and > 10× higher throughput than typical ULV designs. Measurements of 60 dies show modest frequency (energy) σ/μ spreads of 7% (2%).
KW - Fast Fourier Transform (FFT)
KW - subthreshold CMOS circuits
KW - super-pipelining
KW - ultra low voltage (ULV) design
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U2 - 10.1109/JSSC.2011.2169311
DO - 10.1109/JSSC.2011.2169311
M3 - Article
AN - SCOPUS:84655166985
SN - 0018-9200
VL - 47
SP - 23
EP - 34
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 1
M1 - 6069820
ER -