A soft-error hardened process portable embedded microprocessor

Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479986828
StatePublished - Nov 25 2015
EventIEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States
Duration: Sep 28 2015Sep 30 2015


OtherIEEE Custom Integrated Circuits Conference, CICC 2015
Country/TerritoryUnited States
CitySan Jose


  • microprocessor architecture
  • Radiation hardening
  • single event effects
  • soft-errors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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