Abstract
A reduced instruction set computing (RISC) microprocessor was proposed using a six-layer metal 0.18 μm complementary metal oxide semiconductor (CMOS) process. The microprocessor consists of 32 kB instruction and data caches and an 8-entry coalescing writeback buffer. The design was implemented in static CMOS logic and supported full clock stop. Other important aspect of the microprocessor architecture was described in detail.
Original language | English (US) |
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Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
Pages | 230-231 |
Number of pages | 2 |
State | Published - 2001 |
Externally published | Yes |
Event | Digest of Technical Papers - IEEE International Solid-State Circuits Conference - Duration: Feb 5 2001 → Feb 6 2001 |
Other
Other | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
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Period | 2/5/01 → 2/6/01 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering