TY - GEN
T1 - A Scalable and PCB-Friendly Daisy-Chain Approach to Parallelize LDO Regulators with 2.613% Current-Sharing Accuracy Using Dynamic Element Matching for Integrated Current Sensing
AU - Talele, Bhushan
AU - Magod, Raveesh
AU - Kunz, Keith
AU - Manandhar, Sanjeev
AU - Bakkaloglu, Bertan
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/2
Y1 - 2020/2
N2 - A single low-dropout regulator (LDO) for high output current applications presents a challenge for chip-level thermal management and also tends to be inefficient. Straightforward parallelizing of LOOs to increase output current is a flawed approach since subtle variations between devices even with the state-of-the-art manufacturing techniques can cause one of the LDOs to take over the maximum current, and thus enter current limit or thermal shutdown leading to instability and loss of regulation. Parallelizing regulators [1]-[6] to share the high output current equally across each regulator while preserving regulation and stability and to spread the dissipated heat uniformly is thus a challenging design problem.
AB - A single low-dropout regulator (LDO) for high output current applications presents a challenge for chip-level thermal management and also tends to be inefficient. Straightforward parallelizing of LOOs to increase output current is a flawed approach since subtle variations between devices even with the state-of-the-art manufacturing techniques can cause one of the LDOs to take over the maximum current, and thus enter current limit or thermal shutdown leading to instability and loss of regulation. Parallelizing regulators [1]-[6] to share the high output current equally across each regulator while preserving regulation and stability and to spread the dissipated heat uniformly is thus a challenging design problem.
UR - http://www.scopus.com/inward/record.url?scp=85083851327&partnerID=8YFLogxK
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U2 - 10.1109/ISSCC19947.2020.9063144
DO - 10.1109/ISSCC19947.2020.9063144
M3 - Conference contribution
AN - SCOPUS:85083851327
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 494
EP - 496
BT - 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
Y2 - 16 February 2020 through 20 February 2020
ER -