A robust edge encoding technique for energy-efficient multi-cycle interconnect

Jae Sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David Blaauw

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


In this paper, we propose a new circuit technique for on-chip communication, the edge encoding technique, to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2 V 65-nm CMOS technology, the proposed approach achieves up to 34% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 39% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be both larger and more robust to process, voltage, and temperature variations than previous techniques.

Original languageEnglish (US)
Article number5286242
Pages (from-to)264-273
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number2
StatePublished - Feb 2011
Externally publishedYes


  • Bus encoding
  • interconnects
  • on-chip communication
  • repeater
  • variation

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'A robust edge encoding technique for energy-efficient multi-cycle interconnect'. Together they form a unique fingerprint.

Cite this