TY - GEN
T1 - A machine learning resistant strong PUF using subthreshold voltage divider array in 65nm CMOS
AU - Venkatesh, Abilash
AU - Sanyal, Arindam
N1 - Publisher Copyright:
© 2019 IEEE
PY - 2019
Y1 - 2019
N2 - Physically Unclonable Functions (PUFs) are extensively used in hardware security blocks as key-generators and light-weight authentication. With recent advances in machine learning (ML), most existing PUFs are shown to be vulnerable to modeling attacks based on ML algorithms. We present a novel silicon strong PUF architecture that cascades three strong PUFs to implement a single strong PUF that is resistant to ML based modeling attacks. Designed in 65nm CMOS technology, the proposed PUF with 260 challenge response pairs consume 0.43pJ/bit energy consumption from a power supply of 0.8V. The simulated inter-HD and intra-HD of the PUF are 0.5065 and 0.0696 respectively. When subjected to ML based modeling attacks, the prediction accuracy is 60% for logistic regression, artificial neural networking and support vector machine with nonlinear RBF kernel.
AB - Physically Unclonable Functions (PUFs) are extensively used in hardware security blocks as key-generators and light-weight authentication. With recent advances in machine learning (ML), most existing PUFs are shown to be vulnerable to modeling attacks based on ML algorithms. We present a novel silicon strong PUF architecture that cascades three strong PUFs to implement a single strong PUF that is resistant to ML based modeling attacks. Designed in 65nm CMOS technology, the proposed PUF with 260 challenge response pairs consume 0.43pJ/bit energy consumption from a power supply of 0.8V. The simulated inter-HD and intra-HD of the PUF are 0.5065 and 0.0696 respectively. When subjected to ML based modeling attacks, the prediction accuracy is 60% for logistic regression, artificial neural networking and support vector machine with nonlinear RBF kernel.
UR - http://www.scopus.com/inward/record.url?scp=85066804209&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2019.8702525
DO - 10.1109/ISCAS.2019.8702525
M3 - Conference contribution
AN - SCOPUS:85066804209
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Y2 - 26 May 2019 through 29 May 2019
ER -