## Abstract

This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n ^{2}) algorithm and 2) a high complexity O(n ^{2} log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%.

Original language | English (US) |
---|---|

Pages (from-to) | 6-14 |

Number of pages | 9 |

Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |

Volume | 10 |

Issue number | 1 |

DOIs | |

State | Published - Feb 2002 |

## Keywords

- Allocation
- Data-flow graph
- Lagrange multiplier method
- Low power
- Multiple voltages
- Resource and latency constraint
- Scheduling

## ASJC Scopus subject areas

- Software
- Hardware and Architecture
- Electrical and Electronic Engineering