A low complexity heuristic for design of custom network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

72 Scopus citations


Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [1] whose computational complexity is not bounded.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE'06
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)3981080114, 9783981080117
StatePublished - 2006
EventDesign, Automation and Test in Europe, DATE'06 - Munich, Germany
Duration: Mar 6 2006Mar 10 2006

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591


OtherDesign, Automation and Test in Europe, DATE'06

ASJC Scopus subject areas

  • General Engineering


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