Abstract
Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the challenges of resistive NVM CIMs. The proposed CIM macro involves encoding ternary input activations and weights into voltages, and enabling parasitic insensitive charge readout. A power-of-two nonlinear SAR ADC is introduced, designed for energy-efficiency and hardware-friendliness. This ADC employs adaptive conversion skipping based on input voltage, resulting in fine precision for concentrated input levels and coarse conversion for sparse input levels. The proposed FCA-based CIM macro in 180-nm CMOS demonstrates 16times 8 analog MAC operation with an energy efficiency of 1.75 TOPS/W and classification accuracy of 90.2% is obtained for the CIFAR-10 dataset.
Original language | English (US) |
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Pages (from-to) | 70-73 |
Number of pages | 4 |
Journal | IEEE Solid-State Circuits Letters |
Volume | 7 |
DOIs | |
State | Published - 2024 |
Externally published | Yes |
Keywords
- Charge multiply-and-accumulate operation
- compute-in-memory
- ferroelectric capacitor array
- SAR ADC
ASJC Scopus subject areas
- Electrical and Electronic Engineering