TY - JOUR
T1 - A Dividerless Ring Oscillator PLL with 250fs Integrated Jitter Using Sampled Lowpass Filter
AU - Grout, Kevin
AU - Kitchen, Jennifer
N1 - Funding Information:
Manuscript received December 10, 2019; revised February 16, 2020; accepted February 20, 2020. Date of publication February 28, 2020; date of current version November 4, 2020. This work was supported by the Defense Advanced Research Project Agency under Grant D16AP00094. This brief was recommended by Associate Editor G. Torfs. (Corresponding author: Kevin Grout.) The authors are with the Connection One Research Center, Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: kevin.grout.us@ieee.org; kitchen.jennifer@asu.edu).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/11
Y1 - 2020/11
N2 - This brief presents a novel ring oscillator based phase lock loop architecture that is capable of wideband, dividerless integer-N synthesis. The noise transfer function of the presented architecture is the same as a sub-sampling phase lock loop (PLL). Like a sub-sampling PLL, the presented architecture removes the phase detector and charge pump's N^{2} noise that dominates the in-band noise of traditional PLLs. This noise reduction allows the presented ring oscillator PLL to operate with integrated jitter as low as 250fs. Unlike sub-sampling PLLs, the presented architecture moves the sampling block downstream of the loop filter. As the sampled data is lowpass filtered, only low frequency sampling blocks are required, which removes the power and area overheads associated with directly sampling the voltage controlled oscillator. Measurement results show the presented PLL is capable of locking over a wide range of 1.2-2.5GHz. The presented PLL is fabricated in 65nm bulk CMOS, and demonstrates a figure of merit of -242.7dB, which is among best in class for ring oscillator PLLs. Furthermore, an area of 0.0066 mm2 is consumed, which represents the smallest published sub-sampling ring oscillator PLLs.
AB - This brief presents a novel ring oscillator based phase lock loop architecture that is capable of wideband, dividerless integer-N synthesis. The noise transfer function of the presented architecture is the same as a sub-sampling phase lock loop (PLL). Like a sub-sampling PLL, the presented architecture removes the phase detector and charge pump's N^{2} noise that dominates the in-band noise of traditional PLLs. This noise reduction allows the presented ring oscillator PLL to operate with integrated jitter as low as 250fs. Unlike sub-sampling PLLs, the presented architecture moves the sampling block downstream of the loop filter. As the sampled data is lowpass filtered, only low frequency sampling blocks are required, which removes the power and area overheads associated with directly sampling the voltage controlled oscillator. Measurement results show the presented PLL is capable of locking over a wide range of 1.2-2.5GHz. The presented PLL is fabricated in 65nm bulk CMOS, and demonstrates a figure of merit of -242.7dB, which is among best in class for ring oscillator PLLs. Furthermore, an area of 0.0066 mm2 is consumed, which represents the smallest published sub-sampling ring oscillator PLLs.
KW - Phase locked loops
KW - integer-N synthesizers
KW - ring oscillators
KW - sub-sampling PLLs
UR - http://www.scopus.com/inward/record.url?scp=85081373407&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85081373407&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2020.2977025
DO - 10.1109/TCSII.2020.2977025
M3 - Article
AN - SCOPUS:85081373407
SN - 1549-7747
VL - 67
SP - 2337
EP - 2341
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 11
M1 - 9018096
ER -