A Dividerless Ring Oscillator PLL with 250fs Integrated Jitter Using Sampled Lowpass Filter

Kevin Grout, Jennifer Kitchen

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


This brief presents a novel ring oscillator based phase lock loop architecture that is capable of wideband, dividerless integer-N synthesis. The noise transfer function of the presented architecture is the same as a sub-sampling phase lock loop (PLL). Like a sub-sampling PLL, the presented architecture removes the phase detector and charge pump's N^{2} noise that dominates the in-band noise of traditional PLLs. This noise reduction allows the presented ring oscillator PLL to operate with integrated jitter as low as 250fs. Unlike sub-sampling PLLs, the presented architecture moves the sampling block downstream of the loop filter. As the sampled data is lowpass filtered, only low frequency sampling blocks are required, which removes the power and area overheads associated with directly sampling the voltage controlled oscillator. Measurement results show the presented PLL is capable of locking over a wide range of 1.2-2.5GHz. The presented PLL is fabricated in 65nm bulk CMOS, and demonstrates a figure of merit of -242.7dB, which is among best in class for ring oscillator PLLs. Furthermore, an area of 0.0066 mm2 is consumed, which represents the smallest published sub-sampling ring oscillator PLLs.

Original languageEnglish (US)
Article number9018096
Pages (from-to)2337-2341
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number11
StatePublished - Nov 2020


  • Phase locked loops
  • integer-N synthesizers
  • ring oscillators
  • sub-sampling PLLs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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