This paper describes a novel feedback digitization architecture for a digitally controlled PWM DC-DC buck converter. A multi-bit Σ-Δ frequency discriminators (MB-SDFD) is used. This multi-bit parallelization technique is an extension to the first-order Σ-Δ frequency discriminators (SDFD) concept. SDFD concept is based on a non-feedback Σ-Δ modulator that uses FM signal as its input and it outputs stream of bits (ones and zeros) with quantization noise being first-order shaped similar to the traditional Σ-Δ modulators. The output of the multi-bit discriminator is decimated to obtain a higher resolution depending on the output ripple specifications. A block diagram and a behavioral model are presented along with simulation results. Based on 1% allowed output voltage ripple, an 8-bit ADC resolution is achieved using a reference clock frequency of 1MHz. This architecture is flexible and scalable and can fully be implemented in standard digital CMOS.