A Comparison of Systolic Architectures for Matrix Multiplication

Hoon B. Lee, Robert O. Grondin

    Research output: Contribution to journalArticlepeer-review

    2 Scopus citations


    Systolic architectures for matrix multiplication are compared in terms of the maximum speedup which can be achieved with increased processor count in a monolithically integrated circuit. The comparison process integrates the architectural characteristics and the technological parameters. The optimum systolic architecture is found for different limiting factors including switching delay, power dissipation, I/O bandwidth, and clock skew. The interplay between limiting factors is studied through the implementation of an innerproduct step processor using 3-üm CMOS technology and its down-scaled version. For a given chip size and technology there is a critical level of heat extraction which separates a power dissipation limited case from a switching delay limited case.

    Original languageEnglish (US)
    Pages (from-to)285-289
    Number of pages5
    JournalIEEE Journal of Solid-State Circuits
    Issue number1
    StatePublished - Feb 1988

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering


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