A 90 nm bulk CMOS radiation hardened by design cache memory

Xiaoyin Yao; Lawrence T. Clark; Dan W. Patterson; Keith Holbert

doi:10.1109/RADECS.2009.5994698

A 90 nm bulk CMOS radiation hardened by design cache memory

Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith Holbert

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A RHBD high performance cache fabricated on 90 nm bulk CMOS is presented. Test silicon cache data arrays can read and write at 1.02 GHz. Irradiation to 2 Mrad(Si) negligibly impacts standby current. The cache is write-through, and relies on error checking to allow cache invalidation when single event upsets or potential single event transients are detected. The write-through cache architectural state will then naturally be reloaded by the ensuing microprocessor operations. Single cycle invalidation is supported. Single event error ion beam test results are presented, as is a description of measured single event effects in array and peripheral circuits and their mitigation by the design.

Original language	English (US)
Title of host publication	2009 European Conference on Radiation and Its Effects on Components and Systems
Subtitle of host publication	10th RADECS Conference, RADECS 2009
Pages	473-480
Number of pages	8
DOIs	https://doi.org/10.1109/RADECS.2009.5994698
State	Published - Dec 1 2009
Event	2009 10th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2009 - Bruges, Belgium Duration: Sep 14 2009 → Sep 18 2009

Publication series

Name	Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

Other

Other	2009 10th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2009
Country/Territory	Belgium
City	Bruges
Period	9/14/09 → 9/18/09

Keywords

CMOS memory integrated circuits
Radiation hardening
heavy ion beams
high-speed integrated circuits

ASJC Scopus subject areas

Radiation
Electrical and Electronic Engineering

Access to Document

10.1109/RADECS.2009.5994698

Cite this

Yao, X., Clark, L. T., Patterson, D. W., & Holbert, K. (2009). A 90 nm bulk CMOS radiation hardened by design cache memory. In 2009 European Conference on Radiation and Its Effects on Components and Systems: 10th RADECS Conference, RADECS 2009 (pp. 473-480). Article 5994698 (Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS). https://doi.org/10.1109/RADECS.2009.5994698

A 90 nm bulk CMOS radiation hardened by design cache memory. / Yao, Xiaoyin; Clark, Lawrence T.; Patterson, Dan W. et al.
2009 European Conference on Radiation and Its Effects on Components and Systems: 10th RADECS Conference, RADECS 2009. 2009. p. 473-480 5994698 (Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yao, X, Clark, LT, Patterson, DW & Holbert, K 2009, A 90 nm bulk CMOS radiation hardened by design cache memory. in 2009 European Conference on Radiation and Its Effects on Components and Systems: 10th RADECS Conference, RADECS 2009., 5994698, Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS, pp. 473-480, 2009 10th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2009, Bruges, Belgium, 9/14/09. https://doi.org/10.1109/RADECS.2009.5994698

Yao X, Clark LT, Patterson DW, Holbert K. A 90 nm bulk CMOS radiation hardened by design cache memory. In 2009 European Conference on Radiation and Its Effects on Components and Systems: 10th RADECS Conference, RADECS 2009. 2009. p. 473-480. 5994698. (Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS). doi: 10.1109/RADECS.2009.5994698

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AB - A RHBD high performance cache fabricated on 90 nm bulk CMOS is presented. Test silicon cache data arrays can read and write at 1.02 GHz. Irradiation to 2 Mrad(Si) negligibly impacts standby current. The cache is write-through, and relies on error checking to allow cache invalidation when single event upsets or potential single event transients are detected. The write-through cache architectural state will then naturally be reloaded by the ensuing microprocessor operations. Single cycle invalidation is supported. Single event error ion beam test results are presented, as is a description of measured single event effects in array and peripheral circuits and their mitigation by the design.

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A 90 nm bulk CMOS radiation hardened by design cache memory

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Keywords

ASJC Scopus subject areas

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