A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu

Research output: Contribution to journalArticlepeer-review

16 Scopus citations


Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 × 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits.

Original languageEnglish (US)
Article number7390224
Pages (from-to)181-190
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number2
StatePublished - Feb 2016


  • Amplifiers
  • Reconfigurable architectures
  • analog processing circuits
  • design automation
  • design methodology
  • field programmable analog arrays
  • field programmable gate arrays
  • filters

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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