TY - JOUR
T1 - A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter with ±1.5% Frequency and ±3.6% Current-Sharing Error
AU - Sun, Ming
AU - Yang, Zhe
AU - Joshi, Kishan
AU - Mandal, Debashis
AU - Adell, Philippe
AU - Bakkaloglu, Bertan
N1 - Funding Information:
Manuscript received February 25, 2017; revised June 8, 2017; accepted August 20, 2017. Date of publication September 13, 2017; date of current version October 23, 2017. This paper was approved by Associate Editor Pavan Kumar Hanumolu. This work was supported by the NASA/Jet Propulsion Laboratory under Grant 028531-001. (Corresponding author: Ming Sun.) M. Sun, Z. Yang, K. Joshi, D. Mandal, and B. Bakkaloglu are with Arizona State University, Tempe, AZ 85287 USA (e-mail: [email protected]). P. Adell is with the Jet Propulsion Laboratory, Pasadena, CA 91109 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2017.2744618
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2017/11
Y1 - 2017/11
N2 - A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The DC-DC converter achieves 93% peak efficiency for Vi= 2 V and Vo= 1.6 V.
AB - A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The DC-DC converter achieves 93% peak efficiency for Vi= 2 V and Vo= 1.6 V.
KW - Auto zero
KW - DC-DC converter
KW - current sharing
KW - digital frequency synchronization (DFS)
KW - duty-cycle-calibrated delay line (DCC-DL)
KW - hysteretic control
KW - multi-phase buck converter
KW - online offset calibration
KW - phase synchronization
KW - quasi-current mode
KW - switching power supply
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U2 - 10.1109/JSSC.2017.2744618
DO - 10.1109/JSSC.2017.2744618
M3 - Article
AN - SCOPUS:85030328487
SN - 0018-9200
VL - 52
SP - 3081
EP - 3094
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 11
M1 - 8036402
ER -