A 3 GHz wideband Σ Δ fractional-N synthesizer with switched-RC sample-and-hold PFD

H. Hedayati, Bertan Bakkaloglu

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


Designing high linearity phase-frequency-detectors (PFDs) in low-voltage, deep submicrometer processes is a challenging problem. Nonlinear PFDs can fold out of band phase noise, and increase in-band phase noise of fractional-N PLLs in deep submicron processes. A 3-GHz Type-I Σ Δ fractional-N PLL with an exponentially settling voltage-mode switched-RC phase frequency detector (PFD) is presented. A voltage-mode, fully settled switched-RC (SRC)-based sample-and-hold PFD, providing benefits of both an RC loop-filter and a zero-order hold ( ) suppressing reference clock leakage is presented. The exponentially settled SRC PFD is shown to reduce the in-band leakage of quantization noise by 13 dB in comparison to a similar current-mode charge pump PFD, enabling a measured loop-bandwidth of 890-kHz. The fractional-N PLL is fabricated in a 180-nm CMOS technology with 6 metal layers and consumes 18-mA from a 1.8-V power supply. The worst-case near-integer in-band spur is measured at -62 dBc. The measured in-band phase noise at 100-kHz offset from the 3-GHz carrier is -107 dBc/Hz and out-of-band phase noise at 3-MHz offset is -130 dBc/Hz. The phase-locked loop settling time for a frequency step of 45-MHz and 0.1-ppm accuracy is less than 10-μs.

Original languageEnglish (US)
Article number5976425
Pages (from-to)1681-1690
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number9
StatePublished - 2012


  • phase-locked loop (PLL)
  • quantization noise
  • Σ Δ fractional-N synthesizer

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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