This paper presents a low-power SAR ADC with a bidirectional single-side (BSS) switching technique. It reduces the DAC reference power and the total number of unit capacitors by 86% and 75% respectively, compared to the conventional SAR switching technique. It also minimizes the DAC switch driving power as it has only 1 single-side switching event every comparison cycle. Unlike the existing monotonic switching technique that also has only 1 switching event, the comparator input common-mode voltage for the proposed technique does not converge to ground but to Vcm, and thus, obviates the need for a specially designed comparator. To further reduce power, a segmented common-centroid capacitor layout is developed to ensure good matching accuracy. An 11-bit prototype ADC fabricated in 0.18-μm 1P6M CMOS technology achieves an ENOB of 10.3 bits and an SFDR of 77 dB. Operating at 1 MS/s, it consumes only 24 μW from a 1V power supply, leading to a FOM of 19.9 fJ/conv-step.