TY - JOUR
T1 - A 20-MS/s to 40-MS/s reconfigurable pipeline ADC implemented with parallel OTA scaling
AU - Chandrashekar, Kailash
AU - Corsi, Marco
AU - Fattaruso, John
AU - Bakkaloglu, Bertan
N1 - Funding Information:
Manuscript received December 12, 2009; revised February 23, 2010; accepted April 9, 2010. Date of current version August 13, 2010. This work was supported by the High Performance Analog Group, Texas Instruments Incorporated. This paper was recommended by Associate Editor P. Malcovati. K. Chandrashekar and B. Bakkaloglu are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: kailash.chandrashekar@asu.edu). M. Corsi and J. Fattaruso are with the Kilby Laboratory, Texas Instruments Incorporated, Dallas, TX 75251 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2010.2050948 Fig. 1. Block diagram of the reconfigurable pipeline ADC implemented with parallel OTA scaling.
PY - 2010/8
Y1 - 2010/8
N2 - A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18-μ CMOS process and occupies a die area of 1.9μ2.
AB - A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18-μ CMOS process and occupies a die area of 1.9μ2.
KW - Analog-to-digital converter
KW - parallel OTA
KW - power scalable
KW - reconfigurable
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U2 - 10.1109/TCSII.2010.2050948
DO - 10.1109/TCSII.2010.2050948
M3 - Article
AN - SCOPUS:77955794018
SN - 1549-7747
VL - 57
SP - 602
EP - 606
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 8
M1 - 5550467
ER -