A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process

Feng Chen, Srinath Ramaswamy, Bertan Bakkaloglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Scopus citations


A passive switched-capacitor ΣΔ ADC consisting of only switches, capacitors and a comparator, is implemented in a 0.13μm digital CMOS process. This high-speed low-voltage architecture is used in a zero-IF GSM transceiver and has a measured peak SNDR of 67dB over a bandwidth of 100kHz with a SFDR of 75dB and a dynamic range of 72dB. The ADC consumes 1mA from a 1.5V power supply at a clock rate of 104MHz.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsL.C. Fujino, A. Grabel, D. Jeager, K.C. Smith
StatePublished - 2003
Externally publishedYes
Event2003 Digest of Technical Papers - , United States
Duration: Feb 9 2003Feb 13 2003


Other2003 Digest of Technical Papers
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture


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