A 138-TOPS/W Delta-Sigma Modulator-Based Variable- Resolution Activation in-Memory Computing Macro

In-memory computing (1MC) is a widely used technique that performs low-precision computations inside memory elements to break the von-Neumann bottleneck in conventional A1/ML hardware. Recently SRAM based 1MC [1-4] has gained significant attention due to its high energy efficiency and easy integration with CMOS 1Cs. A fundamental limitation of SRAM based 1MC is nonlinearity in the multiply-and-accumulate (MAC) operation. For large values of MAC result, the proportional large discharge current through SRAM bitline pushes the access transistors into linear region and makes the discharge current, and hence the MAC result, a nonlinear function of bitline voltage [1-3]. Recent works have tried to address this fundamental limitation by applying pulsed input activations [3] and adding capacitors to SRAM bitcell [4-5] for charge-domain computation which has much lower sensitivity to bitline voltage, and hence, higher linearity than current-domain computation in traditional SRAM bitcell. While pulsed input makes each SRAM bitcell linear, accumulation of paitial products is still performed in current-domain and the overall MAC result is still nonlinear [3]. The capacitive SRAM in [4-5] improves linearity over current-domain accumulation by making the MAC result independent of the discharge current. However, linearity of MAC is still limited since the analog input is sampled on the capacitor in the bitcell through an NMOS switch. The analog input activation modulates threshold voltage (Vth) of the NMOS switch making the voltage sampled on the capacitor nonlinear. Vth drop in the NMOS capacitor also limits the maximum input swing that can be handled by the SRAM bitcell and restricts the supply voltage to relatively high values.