A 13.2fJ/step 74.3-dB SNDR Pipelined Noise-shaping SAR+VCO ADC

Sumukh Prashant Bhanushali; Arindam Sanyal

doi:10.1109/ESSCIRC59616.2023.10268692

A 13.2fJ/step 74.3-dB SNDR Pipelined Noise-shaping SAR+VCO ADC

Sumukh Prashant Bhanushali, Arindam Sanyal

Engineering, Ira A. Fulton Schools of (IAFSE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work presents an OTA-free pipelined passive noise-shaping SAR (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and 4-36 × lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0. 12mW with SNDR/SFDR of 74.3/S9.ldB at 13. 2fJ/step for OSR of 9.

Original language	English (US)
Title of host publication	ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference
Publisher	IEEE Computer Society
Pages	285-288
Number of pages	4
ISBN (Electronic)	9798350304206
DOIs	https://doi.org/10.1109/ESSCIRC59616.2023.10268692
State	Published - 2023
Event	49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 - Lisbon, Portugal Duration: Sep 11 2023 → Sep 14 2023

Publication series

Name	European Solid-State Circuits Conference
Volume	2023-September
ISSN (Print)	1930-8833

Conference

Conference	49th IEEE European Solid State Circuits Conference, ESSCIRC 2023
Country/Territory	Portugal
City	Lisbon
Period	9/11/23 → 9/14/23

Keywords

inter-stage gain calibration and pipelined ADC
noise-shaping SAR
oversampling ADC
ring VCO

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC59616.2023.10268692

Cite this

A 13.2fJ/step 74.3-dB SNDR Pipelined Noise-shaping SAR+VCO ADC. / Bhanushali, Sumukh Prashant; Sanyal, Arindam.
ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference. IEEE Computer Society, 2023. p. 285-288 (European Solid-State Circuits Conference; Vol. 2023-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Bhanushali, SP & Sanyal, A 2023, A 13.2fJ/step 74.3-dB SNDR Pipelined Noise-shaping SAR+VCO ADC. in ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference. European Solid-State Circuits Conference, vol. 2023-September, IEEE Computer Society, pp. 285-288, 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, 9/11/23. https://doi.org/10.1109/ESSCIRC59616.2023.10268692

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abstract = "This work presents an OTA-free pipelined passive noise-shaping SAR (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and 4-36 × lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0. 12mW with SNDR/SFDR of 74.3/S9.ldB at 13. 2fJ/step for OSR of 9.",

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N2 - This work presents an OTA-free pipelined passive noise-shaping SAR (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and 4-36 × lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0. 12mW with SNDR/SFDR of 74.3/S9.ldB at 13. 2fJ/step for OSR of 9.

AB - This work presents an OTA-free pipelined passive noise-shaping SAR (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and 4-36 × lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0. 12mW with SNDR/SFDR of 74.3/S9.ldB at 13. 2fJ/step for OSR of 9.

KW - inter-stage gain calibration and pipelined ADC

KW - noise-shaping SAR

KW - oversampling ADC

KW - ring VCO

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A 13.2fJ/step 74.3-dB SNDR Pipelined Noise-shaping SAR+VCO ADC

Abstract

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Conference

Keywords

ASJC Scopus subject areas

Access to Document

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