A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

Long Chen; Kareem Ragab; Xiyuan Tang; Jeonggoo Song; Arindam Sanyal; Nan Sun

doi:10.1109/TCSII.2016.2559513

A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, Nan Sun

Research output: Contribution to journal › Article › peer-review

26 Scopus citations

Abstract

This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analogto- digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage V_cm. To remove the nonlinearity due to the comparators' offset mismatch, a simple and effective V_cm-adaptive offset calibration technique is proposed. The prototype ADC in 40-nm CMOS achieves a 35-dB signal to noiseplus- distortion ratio and a 48-dB spurious-free dynamic range at a 700-MS/s sampling rate. It consumes 0.95 mW, leading to a Walden figure-of-merit (FOM) of 30 fJ/conversion-step and a Schreier FOM of 153.4 dB.

Original language	English (US)
Article number	7460902
Pages (from-to)	244-248
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	64
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2016.2559513
State	Published - Mar 2017
Externally published	Yes

Keywords

Analog-to-digital converter (ADC)
high speed
offset calibration
successive approximation register (SAR)

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2016.2559513

Cite this

@article{1814992495f7433983dcf875d8fd1d9b,

title = "A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS",

abstract = "This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analogto- digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage Vcm. To remove the nonlinearity due to the comparators' offset mismatch, a simple and effective Vcm-adaptive offset calibration technique is proposed. The prototype ADC in 40-nm CMOS achieves a 35-dB signal to noiseplus- distortion ratio and a 48-dB spurious-free dynamic range at a 700-MS/s sampling rate. It consumes 0.95 mW, leading to a Walden figure-of-merit (FOM) of 30 fJ/conversion-step and a Schreier FOM of 153.4 dB.",

keywords = "Analog-to-digital converter (ADC), high speed, offset calibration, successive approximation register (SAR)",

author = "Long Chen and Kareem Ragab and Xiyuan Tang and Jeonggoo Song and Arindam Sanyal and Nan Sun",

note = "Funding Information: This work was supported in part by National Science Foundation Grants 1254459, 1509767, and 1527320. This brief was recommended by Associate Editor C. K. Tse. Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2017",

month = mar,

doi = "10.1109/TCSII.2016.2559513",

language = "English (US)",

volume = "64",

pages = "244--248",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

number = "3",

}

TY - JOUR

T1 - A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

AU - Chen, Long

AU - Ragab, Kareem

AU - Tang, Xiyuan

AU - Song, Jeonggoo

AU - Sanyal, Arindam

AU - Sun, Nan

N1 - Funding Information: This work was supported in part by National Science Foundation Grants 1254459, 1509767, and 1527320. This brief was recommended by Associate Editor C. K. Tse. Publisher Copyright: © 2004-2012 IEEE.

PY - 2017/3

Y1 - 2017/3

N2 - This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analogto- digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage Vcm. To remove the nonlinearity due to the comparators' offset mismatch, a simple and effective Vcm-adaptive offset calibration technique is proposed. The prototype ADC in 40-nm CMOS achieves a 35-dB signal to noiseplus- distortion ratio and a 48-dB spurious-free dynamic range at a 700-MS/s sampling rate. It consumes 0.95 mW, leading to a Walden figure-of-merit (FOM) of 30 fJ/conversion-step and a Schreier FOM of 153.4 dB.

AB - This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analogto- digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage Vcm. To remove the nonlinearity due to the comparators' offset mismatch, a simple and effective Vcm-adaptive offset calibration technique is proposed. The prototype ADC in 40-nm CMOS achieves a 35-dB signal to noiseplus- distortion ratio and a 48-dB spurious-free dynamic range at a 700-MS/s sampling rate. It consumes 0.95 mW, leading to a Walden figure-of-merit (FOM) of 30 fJ/conversion-step and a Schreier FOM of 153.4 dB.

KW - Analog-to-digital converter (ADC)

KW - high speed

KW - offset calibration

KW - successive approximation register (SAR)

UR - http://www.scopus.com/inward/record.url?scp=85014636961&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85014636961&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2016.2559513

DO - 10.1109/TCSII.2016.2559513

M3 - Article

AN - SCOPUS:85014636961

SN - 1549-7747

VL - 64

SP - 244

EP - 248

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 3

M1 - 7460902

ER -

A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

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Keywords

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