TY - JOUR
T1 - 21 fJ/step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC
AU - Chandrasekaran, Sanjeev Tannirkulam
AU - Pietri, Stefano
AU - Sanyal, Arindam
N1 - Funding Information:
Manuscript received April 9, 2020; revised July 9, 2020 and August 4, 2020; accepted August 23, 2020. Date of publication August 27, 2020; date of current version September 18, 2020. This article was approved by Associate Editor Andrea Baschirotto. This work was supported by SRC Task 2712.020 through UTD’s Texas Analog Center of Excellence. (Corresponding author: Sanjeev Tannirkulam Chandrasekaran.) Sanjeev Tannirkulam Chandrasekaran and Arindam Sanyal are with the Electrical Engineering Department, University at Buffalo, Buffalo, NY 14260 USA (e-mail: stannirk@buffalo.edu). Stefano Pietri is with NXP Semiconductors, Austin, TX 78735 USA. Digital Object Identifier 10.1109/LSSC.2020.3019784
Publisher Copyright:
© 2018 IEEE.
PY - 2020
Y1 - 2020
N2 - A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this letter. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of the signal band and also have intrinsic interferer rejection capability. A prototype ADC fabricated in 65-nm CMOS is operated at an IF of 52 MHz. The ADC has SNDR of 63.1 and 59.5 dB at 1.04 and 4.3-MHz bandwidth, respectively. The ADC consumes only 0.36-mW power from a 0.9-V supply and has an energy efficiency of 21 fJ/step improving upon the current state of the art by 3.5×.
AB - A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this letter. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of the signal band and also have intrinsic interferer rejection capability. A prototype ADC fabricated in 65-nm CMOS is operated at an IF of 52 MHz. The ADC has SNDR of 63.1 and 59.5 dB at 1.04 and 4.3-MHz bandwidth, respectively. The ADC consumes only 0.36-mW power from a 0.9-V supply and has an energy efficiency of 21 fJ/step improving upon the current state of the art by 3.5×.
KW - Analog-to-digital converter (ADC)
KW - band-pass (BP) delta-sigma (DS)
KW - time interleaved (TI)
KW - voltage-controlled oscillator (VCO)
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U2 - 10.1109/LSSC.2020.3019784
DO - 10.1109/LSSC.2020.3019784
M3 - Article
AN - SCOPUS:85090213876
SN - 2573-9603
VL - 3
SP - 342
EP - 345
JO - IEEE Solid-State Circuits Letters
JF - IEEE Solid-State Circuits Letters
M1 - 9178737
ER -