TY - JOUR
T1 - 0.13pW/Hz Ring VCO-Based Continuous-Time Read-Out ADC for Bio-Impedance Measurement
AU - Danesh, Mohammadhadi
AU - Sanyal, Arindam
N1 - Funding Information:
Manuscript received January 9, 2020; revised February 29, 2020 and March 25, 2020; accepted March 30, 2020. Date of publication April 2, 2020; date of current version November 24, 2020. This work was supported by the Semiconductor Research Corporation through TxACE under Grant Task # 2712.020. This brief was recommended by Associate Editor M. Yavari. (Corresponding author: Arindam Sanyal.) The authors are with the Department of Electrical Engineering, University at Buffalo, Buffalo, NY 14260 USA (e-mail: mdanesh@buffalo.edu; arindams@buffalo.edu).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/12
Y1 - 2020/12
N2 - This brief presents a continuous-time ring voltage-controlled oscillator (VCO)-based second-order $\Delta \Sigma $ analog-to-digital converter (ADC) for bio-impedance measurement. The proposed ADC addresses several limitations of prior works which pre-dominantly use successive approximation register (SAR) ADC, such as kickback noise from sampling circuit and power hungry driver required to drive large sampling capacitance of SAR ADC. A current-reuse architecture is used to reduce power consumption and input-referred noise of the proposed ADC. The ADC is implemented in 65nm CMOS process and used for measuring amplitude and phase of a phantom which models skin impedance. A digital matched filter is used to extract amplitude and phase of the impedance of the phantom. The ADC measures amplitude with a maximum error of 2.8% and measures phase with a maximum error of 0.86° over a frequency range of 1-300 kHz. The ADC has a mean SNR of 67dB with a power efficiency of 0.13pW/Hz which is 9 $\times$ better than state-of-the-art.
AB - This brief presents a continuous-time ring voltage-controlled oscillator (VCO)-based second-order $\Delta \Sigma $ analog-to-digital converter (ADC) for bio-impedance measurement. The proposed ADC addresses several limitations of prior works which pre-dominantly use successive approximation register (SAR) ADC, such as kickback noise from sampling circuit and power hungry driver required to drive large sampling capacitance of SAR ADC. A current-reuse architecture is used to reduce power consumption and input-referred noise of the proposed ADC. The ADC is implemented in 65nm CMOS process and used for measuring amplitude and phase of a phantom which models skin impedance. A digital matched filter is used to extract amplitude and phase of the impedance of the phantom. The ADC measures amplitude with a maximum error of 2.8% and measures phase with a maximum error of 0.86° over a frequency range of 1-300 kHz. The ADC has a mean SNR of 67dB with a power efficiency of 0.13pW/Hz which is 9 $\times$ better than state-of-the-art.
KW - Analog-to-digital converter
KW - bio-impedance
KW - continuous-time ΔΣ
KW - electrical impedance tomography
KW - noise shaping
KW - voltage controlled oscillator (VCO)
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U2 - 10.1109/TCSII.2020.2985336
DO - 10.1109/TCSII.2020.2985336
M3 - Article
AN - SCOPUS:85097089636
SN - 1549-7747
VL - 67
SP - 2823
EP - 2827
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 12
M1 - 9055354
ER -