Abstract
Due to excessive reduction in the gate length, dopant concentrations and the oxide thickness, even the slightest of variations in these quantities can result in significant variations in the performance of a device. This has resulted in a need for efficient and accurate techniques for performing Statistical Analysis of circuits. In this paper 1 we propose a methodology based on Bayesian Networks for computing the exact probability distribution of the delay of a circuit. In case of large circuits where it is not possible to compute the exact distribution, we propose methods to reduce the problem size and get a tight lower bound on the exact distribution.
Original language | English (US) |
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Title of host publication | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers |
Pages | 615-620 |
Number of pages | 6 |
State | Published - 2003 |
Event | IEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers - San Jose, CA, United States Duration: Nov 9 2003 → Nov 13 2003 |
Other
Other | IEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers |
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Country/Territory | United States |
City | San Jose, CA |
Period | 11/9/03 → 11/13/03 |
ASJC Scopus subject areas
- Software