TY - JOUR
T1 - VLSI implementation of discrete wavelet transform
AU - Grzeszczak, Aleksander
AU - Mandal, Mrinal K.
AU - Panchanathan, Sethuraman
AU - Yeap, Tet
N1 - Funding Information:
Manuscript received August 15, 1996. This work was supported by the Microelectronics Network (Micronet) under the Network Centers of Excellence (NCE) program of the Government of Canada. The authors are with the Visual Computing and Communications Laboratory, Department of Electrical Engineering, University of Ottawa, Ottawa, Ont. K1N 6N5, Canada. Publisher Item Identifier S 1063-8210(96)08474-0.
PY - 1996
Y1 - 1996
N2 - This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of multipliers. In addition, it requires a small on-chip interface circuitry for interconnection to a standard communication bus. A detailed analysis of the effect of finite precision of data and wavelet filter coefficients on the accuracy of the DWT coefficients is presented. The architecture has been simulated in VLSI and has a hardware utilization efficiency of 87.5%. Being systolic in nature, the architecture can compute DWT at a data rate of N × 106 samples/s corresponding to a clock speed of N MHz.
AB - This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of multipliers. In addition, it requires a small on-chip interface circuitry for interconnection to a standard communication bus. A detailed analysis of the effect of finite precision of data and wavelet filter coefficients on the accuracy of the DWT coefficients is presented. The architecture has been simulated in VLSI and has a hardware utilization efficiency of 87.5%. Being systolic in nature, the architecture can compute DWT at a data rate of N × 106 samples/s corresponding to a clock speed of N MHz.
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U2 - 10.1109/92.544407
DO - 10.1109/92.544407
M3 - Article
AN - SCOPUS:0030387823
SN - 1063-8210
VL - 4
SP - 421
EP - 433
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 4
ER -