VLSI implementation of adaptive bit/serial IIR filters

Rajeev Badyal; Sayfe Kiaei

VLSI implementation of adaptive bit/serial IIR filters

Rajeev Badyal
, Sayfe Kiaei

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A new structure for the VLSI implementation of a bit/serial adaptive IIR filter is presented. The system is built at a bit level consisting of only gated full adders. This approach allows recursive operation of the IIR filter to be implemented with minimal delay time and chip area. The coefficients of the filter can be updated in real time for the time invariant and adaptive filtering. The fourth-order filter is implemented on a 2-μm CMOS technology clocked at 50 MHz.

Original language	English (US)
Title of host publication	IEEE Pacific RIM Conf Commun Comput Signal Process
Editors	Anon
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	650-652
Number of pages	3
State	Published - 1989
Externally published	Yes
Event	IEEE Pacific RIM Conference on Communications, Computers and Signal Processing - Victoria, BC, Canada Duration: Jun 1 1989 → Jun 2 1989

Other

Other	IEEE Pacific RIM Conference on Communications, Computers and Signal Processing
City	Victoria, BC, Canada
Period	6/1/89 → 6/2/89

ASJC Scopus subject areas

General Engineering

Cite this

@inproceedings{8b2beb3408d54ca29b2af755630deab7,

title = "VLSI implementation of adaptive bit/serial IIR filters",

abstract = "A new structure for the VLSI implementation of a bit/serial adaptive IIR filter is presented. The system is built at a bit level consisting of only gated full adders. This approach allows recursive operation of the IIR filter to be implemented with minimal delay time and chip area. The coefficients of the filter can be updated in real time for the time invariant and adaptive filtering. The fourth-order filter is implemented on a 2-μm CMOS technology clocked at 50 MHz.",

author = "Rajeev Badyal and Sayfe Kiaei",

year = "1989",

language = "English (US)",

pages = "650--652",

editor = "Anon",

booktitle = "IEEE Pacific RIM Conf Commun Comput Signal Process",

publisher = "Publ by IEEE",

note = "IEEE Pacific RIM Conference on Communications, Computers and Signal Processing ; Conference date: 01-06-1989 Through 02-06-1989",

}

TY - GEN

T1 - VLSI implementation of adaptive bit/serial IIR filters

AU - Badyal, Rajeev

AU - Kiaei, Sayfe

PY - 1989

Y1 - 1989

N2 - A new structure for the VLSI implementation of a bit/serial adaptive IIR filter is presented. The system is built at a bit level consisting of only gated full adders. This approach allows recursive operation of the IIR filter to be implemented with minimal delay time and chip area. The coefficients of the filter can be updated in real time for the time invariant and adaptive filtering. The fourth-order filter is implemented on a 2-μm CMOS technology clocked at 50 MHz.

AB - A new structure for the VLSI implementation of a bit/serial adaptive IIR filter is presented. The system is built at a bit level consisting of only gated full adders. This approach allows recursive operation of the IIR filter to be implemented with minimal delay time and chip area. The coefficients of the filter can be updated in real time for the time invariant and adaptive filtering. The fourth-order filter is implemented on a 2-μm CMOS technology clocked at 50 MHz.

UR - https://www.scopus.com/pages/publications/0024943814

UR - https://www.scopus.com/pages/publications/0024943814#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:0024943814

SP - 650

EP - 652

BT - IEEE Pacific RIM Conf Commun Comput Signal Process

A2 - Anon, null

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - IEEE Pacific RIM Conference on Communications, Computers and Signal Processing

Y2 - 1 June 1989 through 2 June 1989

ER -

VLSI implementation of adaptive bit/serial IIR filters

Abstract

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ASJC Scopus subject areas

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