VLSI architecture of a scalable matrix transposer

O. Fatemi; S. Panchanathan

doi:10.1109/ICISS.1996.552445

VLSI architecture of a scalable matrix transposer

O. Fatemi
, S. Panchanathan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

In this paper, we present an ASIC implementation of Matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8×8 matrix cannot be directly obtained from a 4×4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.

Original language	English (US)
Title of host publication	Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
Publisher	IEEE
Pages	382-391
Number of pages	10
ISBN (Print)	0780336399
DOIs	https://doi.org/10.1109/ICISS.1996.552445
State	Published - 1996
Externally published	Yes
Event	Proceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon - Austin, TX, USA Duration: Oct 9 1996 → Oct 11 1996

Other

Other	Proceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon
City	Austin, TX, USA
Period	10/9/96 → 10/11/96

ASJC Scopus subject areas

Condensed Matter Physics
Electrical and Electronic Engineering
Hardware and Architecture

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10.1109/ICISS.1996.552445

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title = "VLSI architecture of a scalable matrix transposer",

abstract = "In this paper, we present an ASIC implementation of Matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8×8 matrix cannot be directly obtained from a 4×4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.",

author = "O. Fatemi and S. Panchanathan",

year = "1996",

doi = "10.1109/ICISS.1996.552445",

language = "English (US)",

isbn = "0780336399",

pages = "382--391",

booktitle = "Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon",

publisher = "IEEE",

note = "Proceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon ; Conference date: 09-10-1996 Through 11-10-1996",

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AU - Panchanathan, S.

PY - 1996

Y1 - 1996

N2 - In this paper, we present an ASIC implementation of Matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8×8 matrix cannot be directly obtained from a 4×4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.

AB - In this paper, we present an ASIC implementation of Matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8×8 matrix cannot be directly obtained from a 4×4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.

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UR - https://www.scopus.com/pages/publications/0030384316#tab=citedBy

U2 - 10.1109/ICISS.1996.552445

DO - 10.1109/ICISS.1996.552445

M3 - Conference contribution

AN - SCOPUS:0030384316

SN - 0780336399

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EP - 391

BT - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon

PB - IEEE

T2 - Proceedings of the 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon

Y2 - 9 October 1996 through 11 October 1996

ER -

VLSI architecture of a scalable matrix transposer

Abstract

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