Ultra-low power radiation hardened by design memory circuits

A 32 × 18 bit ultra-low power radiation-hardened by design (RHBD) register file is fabricated on a 130-nm bulk CMOS technology. Register file readout circuitry allows functionality down to V _DD = 206 mV. Dual interlocked cell (DICE) storage provides SEU immunity above V _DD = 450 mV in accelerated heavy ion testing. This memory is compared to a larger one using identical ultra low voltage circuit design techniques, but un-hardened, i.e., with conventional latch storage and using only two-edge transistor layout and no guard rings. The un-hardened ultra low voltage memory exhibits 100 × lower leakage post-irradiation to 500 krad(Si), when irradiated and measured at V _DD = 500 mV, than when irradiated and measured with V _DD = 1.2 V. Hence, for ultra-low power, ultra-low V _DD circuits, TID hardening techniques may be unnecessary. Read energy dissipated by the RHBD memory is 10.3 f J per bit per operation when operated at 320 mV. The maximum operating frequency is 5 MHz at the same supply voltage.