Ultra-low power analog multiplier based on translinear principle

Mohammadhadi Danesh; Akshay Jayaraj; Sanjeev Tannirkulam Chandrasekaran; Arindam Sanyal

doi:10.1109/ISCAS.2019.8702330

Ultra-low power analog multiplier based on translinear principle

Mohammadhadi Danesh, Akshay Jayaraj, Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

In this paper, a wide dynamic range, current-mode four-quadrant analog multiplier circuit is proposed that utilizes MOS translinear principle. The proposed multiplier is designed in 65nm technology using CMOS transistors operating in weak inversion. A thorough analysis of the proposed design is performed using Spectre and monte-carlo simulations. The multiplier consumes a low power of 0.48µW and supports an input range of ±200nA while operating from 0.8V supply and exhibits an average total harmonic distortion (THD) 1.12%. Post layout simulation results show a high figure-of-merit (FoM) of 1302 verifying superiority of our design against other state-of-the-art multiplier circuits.

Original language	English (US)
Title of host publication	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728103976
DOIs	https://doi.org/10.1109/ISCAS.2019.8702330
State	Published - 2019
Externally published	Yes
Event	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan Duration: May 26 2019 → May 29 2019

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2019-May
ISSN (Print)	0271-4310

Conference

Conference	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Country/Territory	Japan
City	Sapporo
Period	5/26/19 → 5/29/19

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2019.8702330

Cite this

Danesh, M., Jayaraj, A., Chandrasekaran, S. T., & Sanyal, A. (2019). Ultra-low power analog multiplier based on translinear principle. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings Article 8702330 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2019.8702330

Ultra-low power analog multiplier based on translinear principle. / Danesh, Mohammadhadi; Jayaraj, Akshay; Chandrasekaran, Sanjeev Tannirkulam et al.
2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702330 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Danesh, M, Jayaraj, A, Chandrasekaran, ST & Sanyal, A 2019, Ultra-low power analog multiplier based on translinear principle. in 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings., 8702330, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 5/26/19. https://doi.org/10.1109/ISCAS.2019.8702330

Danesh M, Jayaraj A, Chandrasekaran ST, Sanyal A. Ultra-low power analog multiplier based on translinear principle. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8702330. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2019.8702330

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abstract = "In this paper, a wide dynamic range, current-mode four-quadrant analog multiplier circuit is proposed that utilizes MOS translinear principle. The proposed multiplier is designed in 65nm technology using CMOS transistors operating in weak inversion. A thorough analysis of the proposed design is performed using Spectre and monte-carlo simulations. The multiplier consumes a low power of 0.48µW and supports an input range of ±200nA while operating from 0.8V supply and exhibits an average total harmonic distortion (THD) 1.12%. Post layout simulation results show a high figure-of-merit (FoM) of 1302 verifying superiority of our design against other state-of-the-art multiplier circuits.",

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AB - In this paper, a wide dynamic range, current-mode four-quadrant analog multiplier circuit is proposed that utilizes MOS translinear principle. The proposed multiplier is designed in 65nm technology using CMOS transistors operating in weak inversion. A thorough analysis of the proposed design is performed using Spectre and monte-carlo simulations. The multiplier consumes a low power of 0.48µW and supports an input range of ±200nA while operating from 0.8V supply and exhibits an average total harmonic distortion (THD) 1.12%. Post layout simulation results show a high figure-of-merit (FoM) of 1302 verifying superiority of our design against other state-of-the-art multiplier circuits.

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Ultra-low power analog multiplier based on translinear principle

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