Ultra-low energy reconfigurable spintronic threshold logic gate

Deliang Fan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations


This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current mode weighted summation of binary inputs, whereas, the low voltage spintronic threshold device carries out the thresholding operation in an energy efficient manner. The proposed STLG can operate at a small terminal voltage of ∼50mV, resulting in ultra-low energy consumption. The device-circuit simulation results for common benchmarks show that the proposed STLG circuit can achieve 87.5% and 11.1% energy reduction compared with state-of-the-art CMOS look-up-table (LUT) and Memristive Threshold Logic Gate (MTLG) respectively. The ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared with MTLG design.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2016 - Proceedings of the 2016 ACM Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Number of pages4
ISBN (Electronic)9781450342742
StatePublished - May 18 2016
Externally publishedYes
Event26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016 - Boston, United States
Duration: May 18 2016May 20 2016

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Other26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016
Country/TerritoryUnited States


  • Magnetic domain wall strip
  • Magnetic tunnel junction
  • Reconfigurable logic
  • Spintronic
  • Threshold logic

ASJC Scopus subject areas

  • General Engineering


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