Ultra-low energy reconfigurable spintronic threshold logic gate

Deliang Fan

doi:10.1145/2902961.2902994

Ultra-low energy reconfigurable spintronic threshold logic gate

Deliang Fan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current mode weighted summation of binary inputs, whereas, the low voltage spintronic threshold device carries out the thresholding operation in an energy efficient manner. The proposed STLG can operate at a small terminal voltage of ∼50mV, resulting in ultra-low energy consumption. The device-circuit simulation results for common benchmarks show that the proposed STLG circuit can achieve 87.5% and 11.1% energy reduction compared with state-of-the-art CMOS look-up-table (LUT) and Memristive Threshold Logic Gate (MTLG) respectively. The ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared with MTLG design.

Original language	English (US)
Title of host publication	GLSVLSI 2016 - Proceedings of the 2016 ACM Great Lakes Symposium on VLSI
Publisher	Association for Computing Machinery
Pages	385-388
Number of pages	4
ISBN (Electronic)	9781450342742
DOIs	https://doi.org/10.1145/2902961.2902994
State	Published - May 18 2016
Externally published	Yes
Event	26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016 - Boston, United States Duration: May 18 2016 → May 20 2016

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume	18-20-May-2016

Other

Other	26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016
Country/Territory	United States
City	Boston
Period	5/18/16 → 5/20/16

Keywords

Magnetic domain wall strip
Magnetic tunnel junction
Reconfigurable logic
Spintronic
Threshold logic

ASJC Scopus subject areas

General Engineering

Access to Document

10.1145/2902961.2902994

Cite this

Ultra-low energy reconfigurable spintronic threshold logic gate. / Fan, Deliang.
GLSVLSI 2016 - Proceedings of the 2016 ACM Great Lakes Symposium on VLSI. Association for Computing Machinery, 2016. p. 385-388 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. 18-20-May-2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fan, D 2016, Ultra-low energy reconfigurable spintronic threshold logic gate. in GLSVLSI 2016 - Proceedings of the 2016 ACM Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, vol. 18-20-May-2016, Association for Computing Machinery, pp. 385-388, 26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016, Boston, United States, 5/18/16. https://doi.org/10.1145/2902961.2902994

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abstract = "This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current mode weighted summation of binary inputs, whereas, the low voltage spintronic threshold device carries out the thresholding operation in an energy efficient manner. The proposed STLG can operate at a small terminal voltage of ∼50mV, resulting in ultra-low energy consumption. The device-circuit simulation results for common benchmarks show that the proposed STLG circuit can achieve 87.5% and 11.1% energy reduction compared with state-of-the-art CMOS look-up-table (LUT) and Memristive Threshold Logic Gate (MTLG) respectively. The ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared with MTLG design.",

keywords = "Magnetic domain wall strip, Magnetic tunnel junction, Reconfigurable logic, Spintronic, Threshold logic",

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AB - This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current mode weighted summation of binary inputs, whereas, the low voltage spintronic threshold device carries out the thresholding operation in an energy efficient manner. The proposed STLG can operate at a small terminal voltage of ∼50mV, resulting in ultra-low energy consumption. The device-circuit simulation results for common benchmarks show that the proposed STLG circuit can achieve 87.5% and 11.1% energy reduction compared with state-of-the-art CMOS look-up-table (LUT) and Memristive Threshold Logic Gate (MTLG) respectively. The ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared with MTLG design.

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Ultra-low energy reconfigurable spintronic threshold logic gate

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Keywords

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