@inproceedings{200f2130458749d2b498f101281134a4,
title = "Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays",
abstract = "3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 \% under worst-case analyses.",
author = "Chen, \{Hong Yu\} and Bin Gao and Haitong Li and Rui Liu and Peng Huang and Zhe Chen and Bing Chen and Feifei Zhang and Liang Zhao and Zizhen Jiang and Lifeng Liu and Xiaoyan Liu and Jinfeng Kang and Shimeng Yu and Yoshio Nishi and Wong, \{H. S Philip\}",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 34th Symposium on VLSI Technology, VLSIT 2014 ; Conference date: 09-06-2014 Through 12-06-2014",
year = "2014",
month = sep,
day = "8",
doi = "10.1109/VLSIT.2014.6894434",
language = "English (US)",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Digest of Technical Papers - Symposium on VLSI Technology",
}