The Simulation of High-Speed, High-Density Digital Interconnects in Single Chip Packages and Multichip Modules

During the past decade, digital integrated circuits, especially silicon ECL and Gallium Arsenide (GaAs) devices, have become much faster, supporting clock rates of 0.5–2 GHz, and generating off-chip signal rise times as fast as 100 ps. These faster chips are placing considerable pressure on the electrical characteristics of both single chip packages and more recently multichip modules (MCM's), since the packages must be designed not to degrade the performance of the chips themselves. Further, not only must the package assure the integrity of the propagating wavefronts in the package interconnects; the effects of crosstalk, reflections, and other parasitics must all be taken into account simultaneously if the final package design is to be adequate. Because the complexity of the electronic packages under development for high clock rate digital signal processors increasingly overwhelmed the simulation tools which were available to us, we have developed a new, comprehensive electromagnetic (EM) modeling tool, the Networking Algorithm, which is capable of simulating on a digital computer the complexities inherent in real-world interconnects and packages, including simultaneous treatment of the effects of mixed types of transmission line interconnects (i.e., mixtures of stripline, microstrip, and coplanar lines), stubs and branches, reflections, and crosstalk between multiple nets. In this paper we will describe the type of modeling tool which has been developed, discuss the mathematics of the Networking Algorithm, and then present a number of actual examples taken from our high frequency digital package design work to show how such a computer-based EM modeling tool set can assist in the design of high performance packages.