Test selection based on high level fault simulation for mixed-signal systems

Sule Ozev; Alex Orailoglu

Test selection based on high level fault simulation for mixed-signal systems

Sule Ozev
, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.

Original language	English (US)
Title of host publication	Proceedings of the IEEE VLSI Test Symposium
Place of Publication	Los Alamitos, CA, United States
Publisher	IEEE
Pages	149-154
Number of pages	6
State	Published - 2000
Externally published	Yes
Event	18th IEEE VLSI Test Symposium (VTS-2000) - Montreal, Que, Can Duration: Apr 30 2000 → May 4 2000

Other

Other	18th IEEE VLSI Test Symposium (VTS-2000)
City	Montreal, Que, Can
Period	4/30/00 → 5/4/00

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Test selection based on high level fault simulation for mixed-signal systems",

abstract = "Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.",

author = "Sule Ozev and Alex Orailoglu",

year = "2000",

language = "English (US)",

pages = "149--154",

booktitle = "Proceedings of the IEEE VLSI Test Symposium",

publisher = "IEEE",

note = "18th IEEE VLSI Test Symposium (VTS-2000) ; Conference date: 30-04-2000 Through 04-05-2000",

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TY - CHAP

T1 - Test selection based on high level fault simulation for mixed-signal systems

AU - Ozev, Sule

AU - Orailoglu, Alex

PY - 2000

Y1 - 2000

N2 - Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.

AB - Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.

UR - https://www.scopus.com/pages/publications/0033733913

UR - https://www.scopus.com/pages/publications/0033733913#tab=citedBy

M3 - Chapter

AN - SCOPUS:0033733913

SP - 149

EP - 154

BT - Proceedings of the IEEE VLSI Test Symposium

PB - IEEE

CY - Los Alamitos, CA, United States

T2 - 18th IEEE VLSI Test Symposium (VTS-2000)

Y2 - 30 April 2000 through 4 May 2000

ER -

Test selection based on high level fault simulation for mixed-signal systems

Abstract

Other

ASJC Scopus subject areas

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