Survey of STT-MRAM cell design strategies: Taxonomy and sense amplifier tradeoffs for resiliency

Soheil Salehi, Deliang Fan, Ronald F. Demara

Research output: Contribution to journalArticlepeer-review

25 Scopus citations


Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed in this article. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, sense margin, and energy or power consumption costs versus resiliency benefits. Solutions to the reliability issues identified are addressed within a taxonomy created to categorize the current and future approaches to reliable STT-MRAM designs. A variety of destructive and non-destructive sensing schemes are assessed for process variation tolerance, read disturbance reduction, sense margin, and write polarization asymmetry compensation. The highest resiliency strategies deliver a sensing margin above 300mV while incurring low power and energy consumption on the order of picojoules and microwatts, respectively, and attaining read sense latency of a few nanoseconds down to hundreds of picoseconds for non-destructive and destructive sensing schemes, respectively.

Original languageEnglish (US)
Article number48
JournalACM Journal on Emerging Technologies in Computing Systems
Issue number3
StatePublished - Feb 2017
Externally publishedYes


  • Design
  • Magnetic tunnel junction (MTJ)
  • Performance
  • Process variation
  • Read/write reliability
  • Reliability
  • Sense amplifier
  • Spin-transfer torque storage elements

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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