Standby supply voltage minimization for deep sub-micron SRAM

Huifang Qin; Yu Cao; Dejan Markovic; Andrei Vladimirescu; Jan Rabaey

doi:10.1016/j.mejo.2005.03.003

Standby supply voltage minimization for deep sub-micron SRAM

Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan Rabaey

Research output: Contribution to journal › Conference article › peer-review

46 Scopus citations

Abstract

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V_DD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when V_DD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby V_DD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.

Original language	English (US)
Pages (from-to)	789-800
Number of pages	12
Journal	Microelectronics Journal
Volume	36
Issue number	9
DOIs	https://doi.org/10.1016/j.mejo.2005.03.003
State	Published - Sep 2005
Externally published	Yes

Keywords

DRV
Data retention
Leakage suppression
SRAM
State preservation
Variation

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/j.mejo.2005.03.003

Cite this

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title = "Standby supply voltage minimization for deep sub-micron SRAM",

abstract = "Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby VDD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.",

keywords = "DRV, Data retention, Leakage suppression, SRAM, State preservation, Variation",

author = "Huifang Qin and Yu Cao and Dejan Markovic and Andrei Vladimirescu and Jan Rabaey",

year = "2005",

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doi = "10.1016/j.mejo.2005.03.003",

language = "English (US)",

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T1 - Standby supply voltage minimization for deep sub-micron SRAM

AU - Qin, Huifang

AU - Cao, Yu

AU - Markovic, Dejan

AU - Vladimirescu, Andrei

AU - Rabaey, Jan

PY - 2005/9

Y1 - 2005/9

N2 - Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby VDD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.

AB - Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby VDD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.

KW - DRV

KW - Data retention

KW - Leakage suppression

KW - SRAM

KW - State preservation

KW - Variation

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DO - 10.1016/j.mejo.2005.03.003

M3 - Conference article

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EP - 800

JO - Microelectronics Journal

JF - Microelectronics Journal

IS - 9

ER -

Standby supply voltage minimization for deep sub-micron SRAM

Abstract

Keywords

ASJC Scopus subject areas

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