Scalability and design-space analysis of a 1T-1MTJ memory cell

Richard Dorrance; Fengbo Ren; Yuta Toriyama; Amr Amin; C. K. Ken Yang; Dejan Marković

doi:10.1109/NANOARCH.2011.5941480

Scalability and design-space analysis of a 1T-1MTJ memory cell

Richard Dorrance, Fengbo Ren, Yuta Toriyama, Amr Amin, C. K. Ken Yang, Dejan Marković

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.

Original language	English (US)
Title of host publication	Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Pages	32-36
Number of pages	5
DOIs	https://doi.org/10.1109/NANOARCH.2011.5941480
State	Published - 2011
Externally published	Yes
Event	2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 - San Diego, CA, United States Duration: Jun 8 2011 → Jun 9 2011

Publication series

Name	Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Other

Other	2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Country/Territory	United States
City	San Diego, CA
Period	6/8/11 → 6/9/11

Keywords

Design Space
Magnetic Tunnel Junction
STT-RAM
Variability

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/NANOARCH.2011.5941480

Cite this

Dorrance, R., Ren, F., Toriyama, Y., Amin, A., Ken Yang, C. K., & Marković, D. (2011). Scalability and design-space analysis of a 1T-1MTJ memory cell. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 (pp. 32-36). Article 5941480 (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011). https://doi.org/10.1109/NANOARCH.2011.5941480

Scalability and design-space analysis of a 1T-1MTJ memory cell. / Dorrance, Richard; Ren, Fengbo; Toriyama, Yuta et al.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 32-36 5941480 (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dorrance, R, Ren, F, Toriyama, Y, Amin, A, Ken Yang, CK & Marković, D 2011, Scalability and design-space analysis of a 1T-1MTJ memory cell. in Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011., 5941480, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, pp. 32-36, 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, United States, 6/8/11. https://doi.org/10.1109/NANOARCH.2011.5941480

Dorrance R, Ren F, Toriyama Y, Amin A, Ken Yang CK, Marković D. Scalability and design-space analysis of a 1T-1MTJ memory cell. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 32-36. 5941480. (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011). doi: 10.1109/NANOARCH.2011.5941480

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Scalability and design-space analysis of a 1T-1MTJ memory cell

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Keywords

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