Robust timing-aware test generation using pseudo-boolean optimization

Keyphrases

• Chip Fabrication 33%
• Critical Fault 33%
• Delay Faults 33%
• Hazard-free 66%
• Longest Path 33%
• Manufacturing Process 33%
• New Requirements 33%
• On-chip Testing 33%
• Optimization Approach 33%
• Path Length 33%
• Problem Formulation 33%
• Production Test 33%
• Pseudo-Boolean Optimization 100%
• Recent Advances 33%
• Robustness Testing 66%
• Small Delay Defects 33%
• Solving Techniques 33%
• Test Case Generation 100%
• Time-aware 100%

Engineering

• Experimental Result 100%
• Longest Path 100%
• Manufacturing Process 100%
• Pathlength 100%
• Problem Formulation 100%

Computer Science

• Experimental Result 100%
• Longest Path 100%
• Problem Formulation 100%
• Test Generation 100%