Resistive switching random access memory - Materials, device, interconnects, and scaling considerations

Yi Wu; Jiale Liang; Shimeng Yu; Ximeng Guan; H. S.Philip Wong

doi:10.1109/IIRW.2012.6468906

Resistive switching random access memory - Materials, device, interconnects, and scaling considerations

Yi Wu, Jiale Liang, Shimeng Yu, Ximeng Guan, H. S.Philip Wong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

In this paper, we review recent progresses on metal oxide resistive switching memory (RRAM). RRAM device design is explored from different aspects including oxide/electrode materials, uniformity issues, and scaling down to single-digit-nm regime. We studied the stochastic nature of resistive switching in metal oxide RRAM and revealed the physics behind switching parameter variations in HfOx-based RRAM using a 2D analytical solver. In a forward-looking analysis into the sub-10 nm regime, we investigated the impact of wordline/bitline metal wire scaling on the read/write performance, energy consumption in the cross-point memory array architecture.

Original language	English (US)
Title of host publication	2012 IEEE International Integrated Reliability Workshop Final Report, IIRW 2012
Pages	16-21
Number of pages	6
DOIs	https://doi.org/10.1109/IIRW.2012.6468906
State	Published - 2012
Externally published	Yes
Event	2012 IEEE International Integrated Reliability Workshop, IIRW 2012 - South Lake Tahoe, CA, United States Duration: Oct 14 2012 → Oct 18 2012

Publication series

Name	IEEE International Integrated Reliability Workshop Final Report

Other

Other	2012 IEEE International Integrated Reliability Workshop, IIRW 2012
Country/Territory	United States
City	South Lake Tahoe, CA
Period	10/14/12 → 10/18/12

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/IIRW.2012.6468906

Cite this

Wu, Y., Liang, J., Yu, S., Guan, X., & Wong, H. S. P. (2012). Resistive switching random access memory - Materials, device, interconnects, and scaling considerations. In 2012 IEEE International Integrated Reliability Workshop Final Report, IIRW 2012 (pp. 16-21). Article 6468906 (IEEE International Integrated Reliability Workshop Final Report). https://doi.org/10.1109/IIRW.2012.6468906

Resistive switching random access memory - Materials, device, interconnects, and scaling considerations. / Wu, Yi; Liang, Jiale; Yu, Shimeng et al.
2012 IEEE International Integrated Reliability Workshop Final Report, IIRW 2012. 2012. p. 16-21 6468906 (IEEE International Integrated Reliability Workshop Final Report).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wu, Y, Liang, J, Yu, S, Guan, X & Wong, HSP 2012, Resistive switching random access memory - Materials, device, interconnects, and scaling considerations. in 2012 IEEE International Integrated Reliability Workshop Final Report, IIRW 2012., 6468906, IEEE International Integrated Reliability Workshop Final Report, pp. 16-21, 2012 IEEE International Integrated Reliability Workshop, IIRW 2012, South Lake Tahoe, CA, United States, 10/14/12. https://doi.org/10.1109/IIRW.2012.6468906

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abstract = "In this paper, we review recent progresses on metal oxide resistive switching memory (RRAM). RRAM device design is explored from different aspects including oxide/electrode materials, uniformity issues, and scaling down to single-digit-nm regime. We studied the stochastic nature of resistive switching in metal oxide RRAM and revealed the physics behind switching parameter variations in HfOx-based RRAM using a 2D analytical solver. In a forward-looking analysis into the sub-10 nm regime, we investigated the impact of wordline/bitline metal wire scaling on the read/write performance, energy consumption in the cross-point memory array architecture.",

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AB - In this paper, we review recent progresses on metal oxide resistive switching memory (RRAM). RRAM device design is explored from different aspects including oxide/electrode materials, uniformity issues, and scaling down to single-digit-nm regime. We studied the stochastic nature of resistive switching in metal oxide RRAM and revealed the physics behind switching parameter variations in HfOx-based RRAM using a 2D analytical solver. In a forward-looking analysis into the sub-10 nm regime, we investigated the impact of wordline/bitline metal wire scaling on the read/write performance, energy consumption in the cross-point memory array architecture.

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Resistive switching random access memory - Materials, device, interconnects, and scaling considerations

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ASJC Scopus subject areas

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