Reducing transistor variability for high performance low power chips

Robert Rogenmoser; Lawrence T. Clark

doi:10.1109/MM.2013.10

Reducing transistor variability for high performance low power chips

Robert Rogenmoser, Lawrence T. Clark

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance.

Original language	English (US)
Article number	6461870
Pages (from-to)	18-26
Number of pages	9
Journal	IEEE Micro
Volume	33
Issue number	2
DOIs	https://doi.org/10.1109/MM.2013.10
State	Published - 2013
Externally published	Yes

Keywords

CMOS
DDC
VLSI
body bias
deeply depleted channel transistor
low power
undoped channel transistor
voltage scaling

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2013.10

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abstract = "CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance.",

keywords = "CMOS, DDC, VLSI, body bias, deeply depleted channel transistor, low power, undoped channel transistor, voltage scaling",

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AU - Clark, Lawrence T.

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AB - CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance.

KW - CMOS

KW - DDC

KW - VLSI

KW - body bias

KW - deeply depleted channel transistor

KW - low power

KW - undoped channel transistor

KW - voltage scaling

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Reducing transistor variability for high performance low power chips

Abstract

Keywords

ASJC Scopus subject areas

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