Quadtree layouts and I/O bandwidth

S. Bhattacharya; S. Kirani; W. T. Tsai

doi:10.1142/S0129626495000217

Quadtree layouts and I/O bandwidth

S. Bhattacharya
, S. Kirani
, W. T. Tsai

Research output: Contribution to journal › Article › peer-review

Abstract

Quadtree data structure, popular in 2-D applications, has not been studied in the context of VLSI embedding. This paper proposes two generic layout strategies for quadtree layout. Layout attributes are derived with primary focus on area-I/O trade-off. We demonstrate a simple layout mixing strategy to obtain improved boundary I/O characteristics. This is followed by development of a recursive layout mixing strategy which yields an order of improvement.

Original language	English (US)
Pages (from-to)	231-240
Number of pages	10
Journal	Parallel processing letters
Volume	5
Issue number	2
DOIs	https://doi.org/10.1142/S0129626495000217
State	Published - 1995
Externally published	Yes

ASJC Scopus subject areas

Software
Theoretical Computer Science
Hardware and Architecture

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10.1142/S0129626495000217

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title = "Quadtree layouts and I/O bandwidth",

abstract = "Quadtree data structure, popular in 2-D applications, has not been studied in the context of VLSI embedding. This paper proposes two generic layout strategies for quadtree layout. Layout attributes are derived with primary focus on area-I/O trade-off. We demonstrate a simple layout mixing strategy to obtain improved boundary I/O characteristics. This is followed by development of a recursive layout mixing strategy which yields an order of improvement.",

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AU - Tsai, W. T.

PY - 1995

Y1 - 1995

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AB - Quadtree data structure, popular in 2-D applications, has not been studied in the context of VLSI embedding. This paper proposes two generic layout strategies for quadtree layout. Layout attributes are derived with primary focus on area-I/O trade-off. We demonstrate a simple layout mixing strategy to obtain improved boundary I/O characteristics. This is followed by development of a recursive layout mixing strategy which yields an order of improvement.

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UR - https://www.scopus.com/pages/publications/0029311996#tab=citedBy

U2 - 10.1142/S0129626495000217

DO - 10.1142/S0129626495000217

M3 - Article

AN - SCOPUS:0029311996

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SP - 231

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JO - Parallel processing letters

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Quadtree layouts and I/O bandwidth

Abstract

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