Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Rakshith Saligram, Wriddhi Chakraborty, Ningyuan Cao, Yu Cao, Suman Datta, Arijit Raychowdhury

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high-k metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO)-59% (NAND3-RO) higher performance under iso-VDD scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.

Original languageEnglish (US)
Pages (from-to)193-200
Number of pages8
JournalIEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Issue number2
StatePublished - Dec 1 2021


  • Berkeley Short-channel IGFET Model (BSIM)4
  • cryogenic CMOS (Cryo-CMOS)
  • ring oscillators (ROs)
  • standard cells
  • static characteristics
  • threshold voltage
  • transient analysis

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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