Out-of-order issue logic using sorting networks

Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


A fundamental property of superscalar architectures is the execution of multiple instructions per cycle. To accomplish this, the issue logic selects and prioritizes the instructions whose operands will be ready in the next cycle, using wakeup, select and queue update logic. By incorporating the issue logic in one pipeline stage, dependent instructions can be issued in consecutive cycles. However, the many serial operations required makes this problematic from a circuit delay perspective. In this paper, we propose an issue queue design that divides the ready signals into groups, sorts the groups in parallel and provides four oldest ready instructions for issue, with single-cycle operation. Static CMOS select and update logic reduces power and low fan-out in many stages improves circuit speed. The complete issue logic requires 30 inversions, allowing simulated circuit operation at over 3 GHz in a foundry 45nm SOI fabrication process.

Original languageEnglish (US)
Title of host publicationGLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010
Number of pages4
StatePublished - 2010
Event20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI, United States
Duration: May 16 2010May 18 2010

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Conference20th Great Lakes Symposium on VLSI, GLSVLSI 2010
Country/TerritoryUnited States
CityProvidence, RI


  • ILP
  • high speed circuits
  • issue queue
  • micro-architecture
  • out-of-order processing

ASJC Scopus subject areas

  • Engineering(all)


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