On the decreasing significance of large standard cells in technology mapping

Jae Sun Seo; Igor L. Markov; Dennis Sylvester; David Blaauw

doi:10.1109/ICCAD.2008.4681561

On the decreasing significance of large standard cells in technology mapping

Jae Sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

Technology scaling reduces gate delays while wire delays may increase. Our work studies the interaction of this phenomenon with technology mapping and its impact on modern EDA flows. In particular, we demonstrate that the use of larger standard cells increases the number of long wires and may undermine circuit delay optimization at 65nm and below. Experiments with 130nm, 90nm, 65nm, and 45nm industrial CMOS technology suggest that limiting the use of larger standard cells in technology mapping becomes more effective at 65nm and 45nm node, resulting in up to 12% improvement in critical path delay on large benchmark circuits.

Original language	English (US)
Title of host publication	2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008
Pages	116-121
Number of pages	6
DOIs	https://doi.org/10.1109/ICCAD.2008.4681561
State	Published - 2008
Externally published	Yes
Event	2008 International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States Duration: Nov 10 2008 → Nov 13 2008

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)	1092-3152

Other

Other	2008 International Conference on Computer-Aided Design, ICCAD
Country/Territory	United States
City	San Jose, CA
Period	11/10/08 → 11/13/08

ASJC Scopus subject areas

Software
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ICCAD.2008.4681561

Cite this

Seo, J. S., Markov, I. L., Sylvester, D., & Blaauw, D. (2008). On the decreasing significance of large standard cells in technology mapping. In 2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008 (pp. 116-121). Article 4681561 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). https://doi.org/10.1109/ICCAD.2008.4681561

On the decreasing significance of large standard cells in technology mapping. / Seo, Jae Sun; Markov, Igor L.; Sylvester, Dennis et al.
2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008. 2008. p. 116-121 4681561 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Seo, JS, Markov, IL, Sylvester, D & Blaauw, D 2008, On the decreasing significance of large standard cells in technology mapping. in 2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008., 4681561, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, pp. 116-121, 2008 International Conference on Computer-Aided Design, ICCAD, San Jose, CA, United States, 11/10/08. https://doi.org/10.1109/ICCAD.2008.4681561

Seo JS, Markov IL, Sylvester D, Blaauw D. On the decreasing significance of large standard cells in technology mapping. In 2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008. 2008. p. 116-121. 4681561. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). doi: 10.1109/ICCAD.2008.4681561

@inproceedings{75ae8d5275ed491e866bf7225f5894cb,

title = "On the decreasing significance of large standard cells in technology mapping",

abstract = "Technology scaling reduces gate delays while wire delays may increase. Our work studies the interaction of this phenomenon with technology mapping and its impact on modern EDA flows. In particular, we demonstrate that the use of larger standard cells increases the number of long wires and may undermine circuit delay optimization at 65nm and below. Experiments with 130nm, 90nm, 65nm, and 45nm industrial CMOS technology suggest that limiting the use of larger standard cells in technology mapping becomes more effective at 65nm and 45nm node, resulting in up to 12% improvement in critical path delay on large benchmark circuits.",

author = "Seo, {Jae Sun} and Markov, {Igor L.} and Dennis Sylvester and David Blaauw",

year = "2008",

doi = "10.1109/ICCAD.2008.4681561",

language = "English (US)",

isbn = "9781424428205",

series = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD",

pages = "116--121",

booktitle = "2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008",

note = "2008 International Conference on Computer-Aided Design, ICCAD ; Conference date: 10-11-2008 Through 13-11-2008",

}

TY - GEN

T1 - On the decreasing significance of large standard cells in technology mapping

AU - Seo, Jae Sun

AU - Markov, Igor L.

AU - Sylvester, Dennis

AU - Blaauw, David

PY - 2008

Y1 - 2008

N2 - Technology scaling reduces gate delays while wire delays may increase. Our work studies the interaction of this phenomenon with technology mapping and its impact on modern EDA flows. In particular, we demonstrate that the use of larger standard cells increases the number of long wires and may undermine circuit delay optimization at 65nm and below. Experiments with 130nm, 90nm, 65nm, and 45nm industrial CMOS technology suggest that limiting the use of larger standard cells in technology mapping becomes more effective at 65nm and 45nm node, resulting in up to 12% improvement in critical path delay on large benchmark circuits.

AB - Technology scaling reduces gate delays while wire delays may increase. Our work studies the interaction of this phenomenon with technology mapping and its impact on modern EDA flows. In particular, we demonstrate that the use of larger standard cells increases the number of long wires and may undermine circuit delay optimization at 65nm and below. Experiments with 130nm, 90nm, 65nm, and 45nm industrial CMOS technology suggest that limiting the use of larger standard cells in technology mapping becomes more effective at 65nm and 45nm node, resulting in up to 12% improvement in critical path delay on large benchmark circuits.

UR - http://www.scopus.com/inward/record.url?scp=57849139308&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=57849139308&partnerID=8YFLogxK

U2 - 10.1109/ICCAD.2008.4681561

DO - 10.1109/ICCAD.2008.4681561

M3 - Conference contribution

AN - SCOPUS:57849139308

SN - 9781424428205

T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

SP - 116

EP - 121

BT - 2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008

T2 - 2008 International Conference on Computer-Aided Design, ICCAD

Y2 - 10 November 2008 through 13 November 2008

ER -

On the decreasing significance of large standard cells in technology mapping

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this