@article{38edda51f0a747e2beed3fa5449f4294,
title = "Novel Sorting Network-Based Architectures for Rank Order Filters",
abstract = "This paper presents two novel sorting network-based architectures for computing high sample rate nonrecursive rank order filters. The proposed architectures consist of significantly fewer comparators than existing sorting network-based architectures that are based on bubble-sort and Batcher{\textquoteright}s odd-even merge sort. The reduction in the number of comparators is obtained by sorting the columns of the window only once, and by merging the sorted columns in a way such that the number of candidate elements for the output is very small. The number of comparators per output is reduced even further by processing a block of outputs at a time. Block processing procedures that exploit the computational overlap between consecutive windows are developed for both the proposed networks.",
author = "Chaitali Chakrabarti and Wang, {Li Yu}",
note = "Funding Information: There are three classes of architectures for 2-D rank order filters: array-based architectures, stack filter-based architectures and sorting network-based architectures. Reference [ 121 gives an excellent survey of these architectures. The existing array architectures consist of an array of IC2 processors, and either compute an output every K sample periods by having 3 comparators in each processor [6], [8], or compute an output every sample period by having K + 1 comparators in each processor [3]. If an output is to be computed every sample period, then the large area of the array architecture makes such a design impractical. Bit-parallel implementations of Manuscript received August 20, 1993; revised March 7, 1994 and July 12, 1994. This work was supported in part by a Grant from the NSF MIP-9309504. The authors are with the Department of Electrical Engineering, Telecommunications Research Center, Arizona State University, Tempe, A2 85287 USA. IEEE Log Number 9405515.",
year = "1994",
month = dec,
doi = "10.1109/92.335027",
language = "English (US)",
volume = "2",
pages = "502--507",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",
}