Noise-margin analysis of a-Si:H digital circuits

Zi Li, Sameer Venugopal, Rahul Shringarpure, David Allee, Lawrence T. Clark

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


The noise margin is one of the fundamental metrics in evaluating the viability and robustness of digital circuits. An analytical model of amorphous-silicon digital-circuit noise margin was developed, including the effects of circuit aging. The threshold voltage of a-Si:H transistors increases over time with electrical stress, degrading the performance and eventually leading to circuit wear-out. Since static and dynamic inverters are the basic digital-circuit design elements, they are the basis for this analysis. The analytical model is verified with experimental measurements. The lifetime of dynamic a-Si:H digital circuits is found to exceed the lifetime for static a-Si:H circuits by a factor of 2-3. Although the lifetimes are relatively short (∼105 sec) and under continuous electrical stress, they are sufficient for low-duty-cycle applications.

Original languageEnglish (US)
Pages (from-to)251-259
Number of pages9
JournalJournal of the Society for Information Display
Issue number4
StatePublished - Apr 2007


  • Amorphous-silicon thin-film transistors
  • Circuit aging
  • Noise margin
  • Threshold-voltage shift

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Electrical and Electronic Engineering


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