NBTI-aware circuit node criticality computation

Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable effort on accurate modeling and characterization of circuit delay degradation caused by NBTI at different design levels. The search for techniques and methodologies which can aid in effectively minimizing the NBTI effect on circuit delay is still underway. In this work, we present the usage of node criticality computation to drive NBTIaware timing analysis and optimization. Circuits that have undergone this optimization flow show strong resistance to NBTI delay degradation. For the first time, this work proposes a node criticality computation algorithm under an NBTI-aware timing analysis and optimization framework. Our work provides answers to the following yet unaddressed questions: (a) what is the definition of node criticality in a circuit under the NBTI effect? (b) how do we identify the critical nodes that, once protected, will be immune to NBTI timingdegradation? and (c) what are the NBTI effect attenuation approaches? Experimental results indicate that by protecting the critical nodes found by our proposed methodology, circuit delay degradation can be reduced by up to 50%. Combined with peak temperature reduction, the delay degradation can be be further improved.

Original languageEnglish (US)
Article number23
JournalACM Journal on Emerging Technologies in Computing Systems
Issue number3
StatePublished - 2013


  • Circuit aging and reliability
  • Computer-aided design
  • Negative bias temperature instability
  • Node criticality computation
  • Timing analysis and optimization

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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