Modeling and minimization of PMOS NBTI effect for robust nanometer design

Rakesh Vattikonda, Wenping Wang, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

356 Scopus citations

Abstract

Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the degradation of NBTI in both static and dynamic operations. Model scalability and generality are comprehensively verified with experimental data over a wide range of process and bias conditions. By implementing the new model into SPICE for an industrial 90nm technology, key insights are obtained for the development of robust design solutions: (1) the most effective techniques to mitigate the NBTI degradation are VDD tuning, PMOS sizing, and reducing the duty cycle; (2) an optimal VDD exists to minimize the degradation of circuit performance; (3) tuning gate length or the switching frequency has little impact on the NBTI effect; (4) a new switching scenario is identified for worst case timing analysis during NBTI stress.

Original languageEnglish (US)
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1047-1052
Number of pages6
ISBN (Print)1595933816, 1595933816, 9781595933812
DOIs
StatePublished - 2006
Event43rd Annual Design Automation Conference, DAC 2006 - San Francisco, CA, United States
Duration: Jul 24 2006Jul 28 2006

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference43rd Annual Design Automation Conference, DAC 2006
Country/TerritoryUnited States
CitySan Francisco, CA
Period7/24/067/28/06

Keywords

  • NBTI
  • Performance degradation
  • Reliability
  • Temperature
  • Threshold voltage
  • Variability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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